A clock allows gain positions to move with one push of the button. It does get used. Microprocessor control wasn't needed. The clock oscillator frequency adjusts from 12 to 35khz. It is then divided by a factor of 4096 in the 4040.

The oscillator was moved to the power supply board, so the trimmer would be accessible. Its negative voltage is connected to the gates preventing it from functioning except while switching and thereby keeping the oscillator noise out of the rest of the circuitry.

The gating has some tricky requirements, because some gates have to be activated before the signal goes through. The signal was therefore delayed with a flip flop (chip 20). The delay circuitry is shown below. The NOR gate going into it is a leftover gate functioning as an inverter.

The 5 pin of the 4029 prevents further counting when it is high. It rests high; and only when a count is being added does it go low. One of its functions here is to prevent the counts from going beyond the desired end points. The end point signals come out of the decoders as lows, when the highest or lowest gain positions are reached. With a rotary switch being used as a gain limiter, the upper signal comes from the center pin of it. But it would normally be omitted; and the upper signal would come from the 9 pin of the decoder, when eight gain positions are used. The upper and lower end point signals go into different NOR gates, because one is reactivated by an up signal, and the other by a down signal, coming from the switches.

The reset mechanism jams in a predetermined count, as shown later. The transistor circuit attached to it forces the reset during turn on.

Gating the clock is tricky, because it could make a count in one half of a time unit. To prevent that, it should not make a count in its first change of state. The first count is forced by the switch, when the 9 pin of the delay comes down.
 
Here is the delay mechanism:   (Figure)

This delay mechanism requires a clock which sets the delay at one pulse plus a little additional time which occurs betwen the start and the first up motion by it. If the oscillator is omitted, the delay could be produced by running the signal through several gates. About six inverters would probably be the best method. Four might suffice; but it would be risky.
 
A simplified form of the gating is shown below. This circuit has not been tested as such; so one might leave a little extra space on the board for debugging. (Figure)

Here's a general delay mechanism:

The general delay mechanism can be used with any gates. The AND gates are not an essential part of it. The resistor and capacitor would substitute for the six inverters.
 
To use just one up and one down switch for both channels, omitt one counter and one decoder, and fan out from the remaining decoder. Here are the decoder pinouts:   (Figure)

The gain position that occurs upon reset is determined by a binary code on the jam inputs. The left side picks up the code from the right side. A quad pc switch was used for setting the code. The switch was located near the edge of the board for accessing, since there were two boards above it. When the switches are open, resistors to the negative voltage create low signals. For example, to reset the counters to the fourth gain position, the binary code for three is used (0011).

If reset is not used, the 1 pins of the 4029s are fixed low; and the four jam inputs are stabilized by connecting to either rail.
 
Here are the pinouts for the line selectors. When 74C901s are driving LEDs, their positive voltage is two diode levels (1.2V) below ground - that is, when the negative voltage is -7.4V. There is then not an excess of reverse voltage on the LEDS.   (Figure)